1. Field
Embodiments of the invention relate to electronic devices, and more particularly, in one or more embodiments, to amplifiers.
2. Description of the Related Technology
Certain electronic devices employ amplifiers to process signals for transmission to an external device or further processing within the devices. Such amplifiers receive an input signal, and generate an output signal having a gain in comparison to the input signal. Among such amplifiers, operational amplifiers (op-amp) and instrumentation amplifiers (in-amp) are used in many applications. Certain operational amplifiers and instrumentation amplifiers are implemented in a multi-stage configuration to enhance gain and/or performance thereof.
In characterizing the frequency response of an operational amplifier or instrumentation amplifier, a gain-bandwidth product (GBWP) can be used. The term “gain-bandwidth product” refers to the product of the open-loop gain of an amplifier and its −3 dB open-loop bandwidth.
The gain-bandwidth product (GBWP) of an amplifier is determined by the position of the dominant pole of the transfer function of the amplifier in the frequency domain. The term “transfer function” refers to a mathematical representation, in terms of spatial or temporal frequency, of the relation between the input and output of an electronic system. The term “dominant pole” refers to a pole in the frequency domain that masks the effects of other poles.
In some instances, the dominant pole (FDOM) of an amplifier can be defined by a compensation capacitor (CCOMP) and a dominant impedance (RDOM) in the amplifier, as expressed in Equation (1) below. The compensation capacitor is typically a capacitor placed at the highest impedance node for frequency compensation for the amplifier, but can be placed in other nodes in the amplifier.
                              F          DOM                =                  1                      2            ⁢                          π              ·                              C                COMP                            ·                              R                DOM                                                                        Equation        ⁢                                  ⁢                  (          1          )                    
However, the gain-bandwidth product GBWP (or the dominant pole) cannot be arbitrarily increased. As the frequency of the GBWP of an amplifier approaches the frequency of the lowest-frequency secondary (or non-dominant) pole in the amplifier frequency response, the stability of the amplifier can be degraded. The maximum achievable frequency (GBWPMAX) of the GBWP can be limited by the position of the lowest frequency non-dominant pole, and can be expressed in Equation (2) below, where FNONDOM is the frequency of the lowest non-dominant pole, and a is a value of 2 to 3.GBWPMAX≅FNONDOM/a  Equation (2)
Operational amplifiers and instrumental amplifiers are typically used in an electronic system in a closed loop or feedback configuration with a specific value of noise gain GCL. In such a configuration, the actual GBWP of the system is a function of the frequency of the dominant pole, the open-loop gain GOL of the amplifier, and the noise gain GCL (assuming that there are no additional poles or zeros in the frequency response below the gain-bandwidth product GBWP). The gain-bandwidth product GBWP can be expressed in Equation (3) below.
                              G          ⁢                                          ⁢          B          ⁢                                          ⁢          W          ⁢                                          ⁢          P                =                                                            F                DOM                            ·                              G                OL                                                    G              CL                                =                                    G              OL                                      2              ⁢                              π                ·                                  C                  COMP                                ·                                  R                  DOM                                ·                                  G                  CL                                                                                        Equation        ⁢                                  ⁢                  (          3          )                    
Unless the value of the noise gain is fixed in the integrated circuit (IC) of the amplifier, it can be usually adjusted by the users by, for example, selecting the values of external gain-setting components, by digital selection if the IC of the amplifier provides a digitally-controllable gain configuration, or the like. At the lowest noise gain, the gain-bandwidth product GBWP of an amplifier is typically the highest, and the phase margin (a measure of stability) is typically the lowest.
Typically, operational amplifiers and instrumental amplifiers are provided with guaranteed stability in a certain range of noise gains greater than some minimum noise gain, GCL—MIN. If the value of the compensation capacitor CCOMP is constant and fixed (for example, when the amplifier IC has a single compensation capacitor), the gain-bandwidth product GBWP is reduced much below its maximum achievable amount GBWPMAX when the values of noise gain GCL are relatively high.
In some amplifier IC designs, a compensation capacitor can be located externally to the amplifier IC, in which case an end user can adjust the value of the compensation capacitor Camp according to the value of the noise gain GCL in order to increase the gain-bandwidth product GBWP. However, that solution adds the additional cost of the external capacitor and complicates the design of the application circuits.
In programmable-gain amplifiers (PGA), the amplifier IC can contain gain setting components (such as resistors) and switches or the like to select any value of the noise gain GCL across a range of pre-defined gain values. Typically, the selection of gain can be performed by a digital programming of the amplifier IC.
In addition to the gain selection, the amplifier IC can also have ability to adjust the gain-bandwidth product GBWP. This can be achieved by a bank of programmable compensation capacitors so that the value of the compensation capacitor CCOMP can be adjusted together with the noise gain GCL in order to maintain or approach the maximum achievable gain-bandwidth product GBWP, that is, GBWPMAX. The bank of capacitors can contain any number of capacitors, and the adjustment of the overall value of compensation capacitor CCOMP can be achieved by digitally controlled analog switches, for example, metal-oxide-semiconductor field effect transistors (MOSFETs), connected to each capacitor in the bank.
Typically, operational amplifiers and instrumentation amplifiers have relatively high values of open loop gain, for example, about 140 to about 180 dB, in order to achieve relatively high precision (for example, relatively low nonlinearity, relatively low gain error, and/or relatively low distortion). In order to achieve such high amounts of open-loop gain, a multi-stage (for example, 2-stage, 3-stage, or 4-stage) amplifier architecture can be used. In some instances, a first stage of such an amplifier can include a gain-enhanced folded-cascode or telescopic cascode topology. A 2-stage amplifier architecture is often used because it can have a bandwidth/power factor advantage compared to the higher stage architectures (for example, 3-stage or 4-stage architecture) in which each additional stage contains an additional non-dominant pole, and consumes additional power.
Referring to FIG. 1A, an electronic system including a conventional 2-stage amplifier will be described. The illustrated 2-stage amplifier 1 can form at least part of an operational amplifier or an instrumentation amplifier.
In the illustrated embodiment, the amplifier 1 includes a first amplifier stage 10, a second amplifier stage 20, a Miller compensation block 30, a first-stage input node 110, a first-stage output node 131, a second-stage input node 120, and a second-stage output node 132. The first amplifier stage 10 is electrically coupled to the Miller compensation block 30 via the first-stage output node 131. The Miller compensation block 30 is electrically coupled to the second amplifier stage 20 via the second-stage output node 132.
The first amplifier stage 10 receives an input signal Vin, for example, in a form of differential voltage signal, at the first-stage input node 110. The first amplifier stage 10 is configured to amplify the input signal Vin with a first gain. In some embodiments, the first gain can be a fixed gain. The first amplifier stage 10 outputs the amplified signal through the first-stage output node 131. In some instances, the first amplifier stage 10 can include a cascode arrangement, and gain enhancing or boosting amplifiers, as will be described in detail in connection with FIG. 3.
The second amplifier stage 20 receives the amplified signal from the first-stage output node 131 of the first amplifier stage 10 at the second-stage input node 120. In FIG. 1A, the second-stage input node 120 is shown to be separate from the first-stage output node 131, but is electrically shorted to the first-stage output node 13. The second amplifier stage 20 is configured to further amplify the amplified signal with a second gain. The second gain can be a fixed gain. In some embodiments, the gain of the system can be adjusted by programming the noise gain GCL, using a programmable resistor network in a feedback circuit around the amplifier 1. The second amplifier stage 20 outputs the further amplified signal as an output signal Vout through the second-stage output node 132.
The Miller compensation block 30 serves to introduce a dominant pole into the open loop frequency response of the amplifier 1. In one example, the Miller compensation block 30 can include a compensation capacitor 141, as shown in FIG. 1B. In the illustrated amplifier circuit, the highest impedance node in the circuit can be the first-stage output node 131. The impedance value at this node can be relatively high, for example, tens of Giga Ohms, in an example in which the first amplifier stage 10 has a cascode arrangement and gain-enhancement amplifiers. The Miller compensation block 30 allows the value of compensation capacitor CCOMP to be reduced by the factor of the gain of the second amplifier stage 20. Another effect of Miller compensation is to lower the output impedance of the amplifier which normally shifts the position of the non-dominant pole at the output of the second amplifier stage 20 to a higher frequency (pole-splitting).
However, if a digital programming of the amplifier bandwidth is desired for the 2-stage amplifier 1, the amplifier 1 can have a conventional Miller compensation block 30A shown in FIG. 2A in place of the Miller compensation block 30 of FIG. 1B. The Miller compensation block 30A includes a bank of additional or selectable compensation capacitors 142 between the nodes 131, 132 through switches 143. A skilled artisan will appreciate that the number of capacitor/switch sets can vary widely, depending on the configuration of the circuit. The switches 143 can be coupled between the left terminals of the additional compensation capacitors 142 and the first-stage output node 131. The switches 143 can be implemented with, for example, MOSFETs. In this case, however, the leakage currents arising from diffusion and channel sub-threshold leakages in the MOSFETs (more noticeable at higher temperatures) can significantly reduce the impedance at the first-stage output node 131, and therefore significantly reduce the value of open loop gain, and introduces offset errors.
FIG. 2B illustrates an example of an alternative Miller compensation block 30B that can be used in place of the Miller compensation block 30 of FIG. 1A. The Miller compensation block 30B includes switches 144 coupled between the right terminals of the additional compensation capacitors 142 and the second-stage input node 120, as shown in FIG. 2B. A skilled artisan will appreciate that the number of capacitor/switch sets can vary widely, depending on the design of the circuit. However, when one or more switches 144 are turned off, the unselected compensation capacitors 142 are left floating. The unselected compensation capacitors 142 can generate undesirable spurious long-settling components in the input offset voltage and in the transient response of the amplifier due to long-settling discharge of the unselected capacitors into the first-stage output node 131 from leakage currents of the switches 144.